1. Technical Field
The invention relates to a refresh technology for dynamic random access memory, to increase a refreshing operation effect.
2. Background
Dynamic random access memory (DRAM) is already commonly used in different circuit system for digital processing, wherein the most common are, for example, computer systems, to store required temporary information during processing. DRAM and static random access memory (SRAM) are both volatile memory. When a power source is off, the information stored in a memory cell disappears. However, the memory cell structure of DRAM is formed through a MOS transistor and a storage capacitor. Thus, the area occupied on the chip is small, and so it is more commonly used.
FIG. 1 is a schematic view of a conventional DRAM memory cell. Referring to FIG. 1, a DRAM memory cell 50 includes a MOS transistor 52 and a storage capacitor 54. A bit line and a source of the transistor 52 are connected. A drain of the MOS transistor 52 is connected to the storage capacitor 54. The other end of the storage capacitor 54 is connected to the ground. A word line and a gate of the transistor 52 are connected. A word line will connect to multiple memory cells 50, and a bit line will also connect to multiple memory cells. Thus, the memory cells 50 compose a two-dimensional memory cell array. Each memory cell will be accessed by a bit line and a word line that are intersecting.
The transistor 52 is described as an NMOS transistor. For example, when writing a “1” information into the storage capacitor 54, the corresponding connected bit line will exert a 5V voltage signal. At this point the corresponding connected word line will exert a starting voltage, which is, for example also 5V, conducted to the transistor 52. Then the voltage of the bit line will charge the storage capacitor 54 to 5V. After that, the transistor 52 can be turned off by a low voltage state of the bit line. The voltage of the bit line is subsequently turned off, or other memory cells 50 are continued to be written into. In contrast, if a “0” information is written, then the bit line will exert a 0V voltage signal. Thus, the voltage of the storage capacitor 54 is 0V. It can be seen that the information “1” or “0” is stored through the high low voltage of the storage capacitor 54.
The following describes a reading mechanism. FIG. 2 illustrates a conventional reading circuit of a memory cell. Referring to FIG. 2, if the information of the memory cell 50 is to be read, the bit line connected to the memory cell 50 selected to be read is switched to a comparator 56. A reference voltage VRef of the comparator 56 is between 0V and 5V. When the bit line is conducted through the memory cell 50, the voltage of the bit line is the voltage V of the storage capacitor, which is 0V or 5V. The voltage V of the storage capacitor 54 can be known to be 0V or 5V by comparing the reference voltage VRef.
In the DRAM memory cell 50 structure, if the storage capacitor 54 stores the “1” information with a high voltage level, the electric charge will leak because of leakage current, lowering the voltage. If the voltage value of the storage capacitor 54 is not refreshed after a long time, wrong information will be produced. Generally, to refresh the voltage value of the storage capacitor 54, reading the voltage value of the storage capacitor 54 refreshes it. The reading operation can be an actual obtaining of the information or a dummy read. When rewriting the storage value the information will naturally be refreshed.
FIG. 3A illustrates a conventional diagram of a mechanism of a distributed refresh mode. Referring to FIG. 3A, generally a time interval will require refreshing n times. Conventional refreshing operations can be at a specific time uniformly distributed in a time interval, to perform a refreshing operation towards the memory cell. This is referred to as a distributed refresh mode. Another refreshing operation is, for example, a burst refresh mode. A pulse represents one refreshing operation. FIG. 3B illustrates a conventional diagram of a mechanism of a burst refresh mode. Referring to FIG. 3B, the burst refresh mode will continuously perform multiple refreshing operations in a time interval.